TY  - GEN
AU  -  Mano, M. Morris
AU  - Ciletti, Michael D
TI  - Digital design: with an introduction to the verilog HDL, VHDL and systemverilog
SN  - 9789353062019			
U1  - 621.395 
PY  - 2019///
CY  - Noida
PB  - Pearson
KW  - Digital system
KW  - Logic gates
KW  - Minimization
KW  - Combinational logic
KW  - Standard graphic symbols
KW  - Registers and counters
N1  - Includes index
ER  -