TY  - BOOK
AU  - Bosschere,Koen De
AU  - Kaeli,David
AU  - Stenstr�m,Per
AU  - Whalley,David
AU  - Ungerer,Theo
ED  - SpringerLink (Online service)
TI  - High Performance Embedded Architectures and Compilers: Second International Conference, HiPEAC 2007, Ghent, Belgium, January 28-30, 2007. Proceedings 
T2  - Lecture Notes in Computer Science,
SN  - 9783540693383
AV  - QA75.5-76.95 
U1  - 004.0151 23
PY  - 2007///
CY  - Berlin, Heidelberg
PB  - Springer Berlin Heidelberg
KW  - Computer science
KW  - Arithmetic and logic units, Computer
KW  - Input-output equipment (Computers)
KW  - Logic design
KW  - Microprocessors
KW  - Computer communication systems
KW  - Computers
KW  - Computer Science
KW  - Theory of Computation
KW  - Arithmetic and Logic Structures
KW  - Processor Architectures
KW  - Input/Output and Data Communications
KW  - Logic Design
KW  - Computer Communication Networks
N1  - Invited Program -- Keynote: Insight, Not (Random) Numbers: An Embedded Perspective -- I Secure and Low-Power Embedded Memory Systems -- Compiler-Assisted Memory Encryption for Embedded Processors -- Leveraging High Performance Data Cache Techniques to Save Power in Embedded Systems -- Applying Decay to Reduce Dynamic Power in Set-Associative Caches -- II Architecture/Compiler Optimizations for Efficient Embedded Processing -- Virtual Registers: Reducing Register Pressure Without Enlarging the Register File -- Bounds Checking with Taint-Based Analysis -- Reducing Exit Stub Memory Consumption in Code Caches -- III Adaptive Microarchitectures -- Reducing Branch Misprediction Penalties Via Adaptive Pipeline Scaling -- Fetch Gating Control Through Speculative Instruction Window Weighting -- Dynamic Capacity-Speed Tradeoffs in SMT Processor Caches -- Branch History Matching: Branch Predictor Warmup for Sampled Simulation -- Sunflower : Full-System, Embedded Microarchitecture Evaluation -- Efficient Program Power Behavior Characterization -- Generation of Efficient Embedded Applications -- Performance/Energy Optimization of DSP Transforms on the XScale Processor -- Arx: A Toolset for the Efficient Simulation and Direct Synthesis of High-Performance Signal Processing Algorithms -- A Throughput-Driven Task Creation and Mapping for Network Processors -- Optimizations and Architectural Tradeoffs for Embedded Systems -- MiDataSets: Creating the Conditions for a More Realistic Evaluation of Iterative Optimization -- Evaluation of Offset Assignment Heuristics -- Customizing the Datapath and ISA of Soft VLIW Processors -- Instruction Set Extension Generation with Considering Physical Constraints
UR  - http://dx.doi.org/10.1007/978-3-540-69338-3
ER  -